About the Project

  • Collaboration with JKU

    • Radar Front-End

    • SAR picture calculation / creation

  • Sampling of the Radar Data

    • 5 GSPS / 14 Bit ADCs of the 4×2 Board

  • Transmission of the Data FPGA -> Jetson/PC

    • Protocol framing & package creation

    • Checksum generation

    • UDP framing

  • FPGA configuration

    • Pynq on SoC

    • Pynq interfaces on FPGA IPs

    • Jupyter – Python

  • Data reception and storage

    • PC (up to 100 GBit/s) or Jetson (up to 10 GBit/s) running Linux

    • CPU forwards data from network interface to SSD via PCIe

Alexander Daum

Linux

Matthias Kern

FPGA

Matthias Possenig

FPGA

Tobias Karrer

FPGA

Contact us

https://fh-ooe.at/campus-hagenberg